linux - CPU L3 cache miss and hit ratio details

24
2013-08
  • Nikesh PL

    How can i see the CPU L3 cache miss and hit ratio details in Rtedhat Linux box?

    • Answers
  • MSalters

    Since it's an Intel CPU, you could try the Intel adaptor that plugs into the KDE utility ksysguard


    • Related Question

    memory - RAM size > L2 Cache size > L1 Cache size > Internal Registers of a CPU
  • S.Man

    I understand that the access speed of internal registers is very high compared to that of L1 Cache and L1 Cache can be accessed faster than that of L2 cache which in turn can be accessed faster than that of RAM . But, i wonder why is the size of Internal registers always less than that of L1 Cache and why is the size of L1 cache mostly less that that of L2 cache which in turn is always less than that of RAM size ?


    • Related Answers
  • Josip Medved

    Mostly because of cost. Faster memory is, it costs more to manufacture. For performance reasons, you want registers to be as fast as possible but you also want to keep cost of processor low. So designer decided on good-enough measure for that memory that keeps cost under control and performance in acceptable range.

    In order to make performance even better somebody decided to make L1 cache with memory that is little bit cheaper but still faster than RAM. Of course, since it is cheaper, we can put it more than registers but still less than cheap RAM. So designer found balance here also.

    And story goes on to Lx cache...

  • egon

    Basically registers are built in with the CPU and therefore can be directly manipulated processing units. If you would want to construct such L1 there would be too much wiring -- also the wire latency would affect the speed of accessing such big registers.

    Also it's expensive to make RAM as fast as L1/L2 cache.

    For more accurate and detailed info on that read What every programmer should know about memory.