computer architecture - How does an instruction in a CPU report that is has finished?

When an instruction is sent to a CPU, that may take multiple clock cycles to complete, when does the CPU know that the instruction has finished and can start processing the next one? I'm mostly interested in RISC architectures for the simplicity, since CISC may contain complex microcode.

Typically, for simple CPUs that are not superscalar and don't have sophisticated pre-fetch or pipeline logic, this is done by an actual circuit connection. When an instruction is retired, a wire from the retire logic to the fetch unit triggers the fetching of the next instruction.