cpu - When a non-vectored interrupt occurs,does the processor ever look up the vector table?

06
2014-04
  • steve

    When a non-vectored interrupt occurs,does the processor ever look up the vector table ?

    Talking of 8085 , is it different ?

    • Answers
  • Breakthrough

    An interrupt address table (otherwise known as "interrupt vector table") allows for the interrupt service routine's location to be changed by software. This only requires the interrupting device to send the ID of the interrupt, which is then used as the offset in the interrupt address table to determine where to relocate the program counter/instruction pointer. This only applies to a vectored interrupt.

    Conversely, in a non-vectored interrupt, the peripheral itself provides the address of the interrupt service routine directly to the processor. This requires more time for an interrupt to be serviced, since the address must be retrieved from the interrupting device every time the interrupt is triggered.


    • Related Question

    cpu - BIOS interrupts, privilege levels and paging
  • Questioner

    I was learning about Intel 8086-80486 CPUs and their interactions with hardware. But I still don´t understand it quite well. Please, help me fill blank spots.

    First, I know that the CPU communicates with hardware using BIOS interrupts. But, what really happens in the PC, when I call some INT instruction? I know that according to the interrupt table some instructions begin to execute, but how, by executing some instructions, can BIOS recognize what I want to do? Because as far as I know, CPU has no extra communication channel with the BIOS, it can only adress memory and receive data. So how can I instruct BIOS to do something, when I can only address RAM?

    Next thing I don't understand is about privilege levels. I know about the ring model, and access rights, but how does the CPU know which privilege level has executed an instruction? I think that these privileges apply only when intruction is trying to address memory, but how does an application get its privilege level? I mean I know its level 3, but how is it set?

    And last thing, I know that paging is an address scheme that is used to support aplication-transparent virtual memory, or swapping, but I could not find any information about how paging is tied with protected mode. Like if paging is like next mode independent of protected mode, or it's somehow implemented within protected mode. And if it is implemented in protected mode, isn't it too slow, to first address application space, then offset, and then paging folder, page and offset once again?


    • Related Answers
  • Tomas Lachman

    There are 2 modes: real and protected. In real mode you can address only 1 MiB of memory. BIOS interrupts are accessible only in real mode. Addresses A0000 - FFFFF are mapped: A0000 - BFFFF is video memory, F0000 - FFFFF is ROM BIOS, where the code of BIOS interrupt service routines is located. There are no privilege levels in real mode. If you execute "int n" instruction, this happens: flags, cs, ip are stored onto the stack. Word at n*4+2 is loaded in cs and word at n*4 is loaded in ip.

    Protected mode is started by setting bit 0 of cr0 register. Then you have the 4 privilege levels. But before starting it, you must enable A20, set interrupt bases of IRQ 0-7 and IRQ 8-15, create IDT, GDT.

    Paging is started by setting bit 31 of cr0. Before starting it you must create page directory and page tables and set cr3 to point to the page directory.