memory - Instruction cache vs data cache with reguards to size
2014-07
Celeritas
In the context of cache for a CPU, I understand some are divided between instructions and for data. How exactly are they divided? Is one physical unit partitioned into two or are there two units containing memory of the same speed?
It's also my understanding that the size of the data cache need not equal the size of the instruction cache. This is where I have a bit of an issue. Someone told me the data cache is usually bigger. Data most likely will be more variable than instructions. I equate more variability with more cache misses and more memory reads. So wouldn't this mean the instruction cache should be bigger, not the data cache? I was told this is not true because having a bigger cache is what remedies the miss-rate. I still feel uneasy about this because unless the cache is substantially bigger than the miss-rate won't be affected that much and the overall performance goes down (it's like having too many layers of cache - is there a name for this? - similar concept to having too many indexes in a SQL database will actually slow it down).
The way I see the question is which would you want to make better? The one that initially works better or the one that initially works worse.
M3taSpl0it
I'm learning about the BIOS and have a few questions.
What is meant by, "This is the last 16 bytes of memory at the end of the first megabyte of memory"?
The first instruction of BIOS is jump, which jumps to the main BIOS program, but where does it jump?
Where does the original BIOS code originate?
I'm also interested in POST? How are POST signals executed by the processor?
t0mm13b
To answer the second question, the bios jumps to 0x7c00 which is the start of the bootsector code (I gather that from debugging and creating bootsectors...) in turn the bootsector is loaded into that offset in memory.
POST is a Power On Self Test, when the BIOS routines execute a check on the hardware devices such as memory, keyboard, disk and screen, it emits a beep if the check fails depending on the device in question such as if the hard disk fails, its 2 beeps, there are variations in the beep to signify the problems at hand. These are quite rare now that BIOS's are more reliable and that the hardware detection is far more reliable then those back then...MFM/RLL drives used to be problematic with the BIOS's unless they are from an iffy batch of disks.... Keyboards with the BIOS are notorious for displaying 'Hit F1 to continue' if there's no keyboards....
Hope this helps, Best regards, Tom.
Ignacio Vazquez-Abrams
- Offsets 0x0ffff0 through 0x0fffff of the computer's physical memory.
- Into BIOS code, which someone has previously written and burned into non-volatile memory.
RChandra
@tommieb75: That is where the processor will eventually jump, but only if the BIOS manages to find a boot sector on an attached peripheral (HDD, properly formatted USB Flash drive, El Torito CD, TFTP from a PXE server, etc.). This boot sector will have the 0x55AA signature at the end of it. The prototypical example is the MBR, which is free to do anything it wants, but again typically looks through the partition table for one (and only one) bootable flag, moves itself from the 0x7C00 address (to where depends on its code), loads that partition's first sector to 0x7C00, and jumps to it. This partition boot sector should also have the 0x55AA signature.
As far as the original question...there is no fixed address to which the processor is instructed by the BIOS ROM to jump; this is dependent on whatever the BIOS author wants. The address of 16 bytes below the end of 1 megabyte is just something hardcoded into the processor itself; this is the documented/defined behavior (by Intel, and by association, AMD and others). Obviously, 16 bytes of code isn't a lot of code, so it's usually just a "long jump" (loading both the CS and IP registers) to somewhere else in the BIOS ROM. That code handles POST and the aforementioned location of a valid boot sector to execute.